1. Field of the Invention
The present invention relates to a sense amplifier, and, more particularly, to a clocked differential CMOS sense amplifier intended for sensing and latching of small-swing differential signals.
2. Description of the Prior Art
There is a wide range of clocked differential sense amplifiers designs available today for sensing small differential signals. Most, however, if not all, use a cross-coupled transistor structure that serves as the basis of the sense amplifier function. The principal differences between these various sense amplifier designs relates to the method of imbalancing in the cross-coupled nodes before or during the strobe pulse edge. An example of present day sense amplifiers for small differential signals can be found in M. Matsui and J. B. Burr xe2x80x9cA Low-Voltage 32 * 32-Bit Multiplier in Dynamic Differential Logicxe2x80x9d 1995 IEEE Symposium on Low Power Electronics, Vol. 1.
A typical prior art sense amplifier circuit 10 used in small signal differential logic (SSDL) is shown in FIG. 1. The timing diagram illustrating operation of the circuit of FIG. 1(a) is shown in FIG. 1B. (In FIG. 1B inputs I and NI and outputs Q and NQ are shown together. The solid lines 12 and 16 are the voltage levels for input I and output Q, respectively, while the dotted lines 14 and 18 are the voltage levels for input NI and output NQ, respectively.)
As FIG. 1A shows, complementary CMOS transistors MP1/MN1 and MP2/MN2 form a pair of cross-coupled inverters as is conventional in such sensing circuits. Transistor MP5, controlled by clock pulse (NCLK), serves as a clocked current source, and transistors MN3, MN4 operate to precharge the cross-coupled output nodes Q and NQ to ground when the current source MN5 is turned off and transistors MN3 and MN4 are turned on by the high level of the NCLK signal. The Transistors MP3, MP4 provide the difference in discharging currents in accordance with any imbalance in the input voltages applied to the input nodes I, NI. The sense phase of the circuit 10 is entered when NCLK goes low to turn on the current source transistor MP5. Inputs I and NI receive the differential signal to be sensed, and the small difference in voltage levels at inputs I and NI will create a difference in discharging currents which, in turn, will cause one of the cross-coupled inverters MP1/MN1, MP2/MN2 to conduct faster than the other, leading to a difference in voltages of output nodes Q and NQ. Because of the positive feedback provided by the cross-coupling between the inverters MP1/MN1 and MP2/MN2, the output node with the higher potential will be pulled even higher, and the other will be pulled back to ground.
While prior art sense amplifiers similar to that shown in FIG. 1A perform their functions well, their dependence on the conductivity of the charging or discharging paths and the capacitance of the cross-coupled nodes can adversely affect speed and loading characteristics. Circuits of the type of FIG. 1A often have a charge/discharge path that includes three p-channel transistors. For example, the charge/discharge paths of the sense amplifier 10 include transistors MP1, MP3, and MP5 (or MP2, MP4, and MP5) connected in series. This use of p-channel transistors in a current path can tend to limit conductivity.
In addition, the capacitance of each of the cross-coupled nodes include (1) the drain capacitance of the one p- and n-channel cross-coupled transistor pair and (2) the gate capacitance of the opposite pair and the drain capacitance of recovery transistor MN3 (MN4). In order to ensure to establish sharp rising edges of the output signals at outputs Q and NQ, the p-channel transistors MP1 and MP2 must be relatively large. This, however, requires the p-channel transistors to be made larger, using expensive semiconductor real estate.
The present invention provides a CMOS clocked sense amplifier that provides high speed sensing of low-swing complementary signals. Broadly, the sense amplifier of the present invention includes a controlled latch for sensing and amplifying the differential input, a control circuit, and recovery circuit. The latch includes a pair of cross-coupled CMOS inverters each having individual controlled current paths to ground provided by the control circuit. The control circuit includes sense inputs to receive the differential signal and a clock input to receive the clock signal that functions as a sense strobe, alternately switching the amplifier between a sense state and a pre-charge state. An acceleration transistor couples the sense inputs to one another to discharge and equalize the inputs when the clock signal is in a pre-charge state. The sense amplifier is structured so that only two n-channel transistors form a discharge path for the inputs, to provide a high-speed output of the sense amplifier.